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HV9910B Universal High Brightness LED Driver
Features
Switch mode controller for single switch LED drivers Enhanced drop-in replacement to the HV9910 Open loop peak current controller Internal 8.0 to 450V linear regulator Constant frequency or constant off-time operation Linear and PWM dimming capability Requires few external components for operation
General Description
The HV9910B is an open loop, current mode, control LED driver IC. The HV9910B can be programmed to operate in either a constant frequency or constant off-time mode. It includes an 8.0 - 450V linear regulator which allows it to work from a wide range of input voltages without the need for an external low voltage supply. The HV9910B includes a PWM dimming input that can accept an external control signal with a duty ratio of 0 - 100% and a frequency of up to a few kilohertz. It also includes a 0 - 250mV linear dimming input which can be used for linear dimming of the LED current. The HV9910B is ideally suited for buck LED drivers. Since the HV9910B operates in open loop current mode control, the controller achieves good output current regulation without the need for any loop compensation. PWM dimming response is limited only by the rate of rise and fall of the inductor current, enabling very fast rise and fall times. The HV9910B requires only three external components (apart from the power stage) to produce a controlled LED current making it an ideal solution for low cost LED drivers.
Applications
DC/DC or AC/DC LED driver applications RGB backlighting LED driver Back lighting of flat panel displays General purpose constant current source Signage and decorative LED lighting Chargers
Typical Application Circuit
CIN D1 CDD VDD L1 VIN CO
HV9910B
LD PWMD RT GATE CS GND RCS Q1
RT
HV9910B
Ordering Information
Package Options Device HV9910B 8-Lead SOIC HV9910BLG-G 16-Lead SOIC HV9910BNG-G
VIN 1 NC 2 NC 3 CS 4 VIN 1 CS 2 GND 3 GATE 4 8 7 6 5 RT LD VDD PWMD GND 5 NC 6 NC 7 GATE 8 16 15 14 13 12 11 10 9 NC NC RT LD VDD NC NC PWMD
Pin Description
-G indicates package is RoHS compliant (`Green')
Absolute Maximum Ratings
Parameter VIN to GND VDD to GND CS, LD, PWMD, GATE, RT to GND Junction temperature range Storage temperature range Continuous power dissipation
(TA = +25C)
Value -0.5V to +470V 12V -0.3V to (VDD +0.3V) -40C to +150C -65C to +150C
8-Lead SOIC (LG)
16-Lead SOIC (NG)
Product Marking
YWW
9910B
LLLL
Y = Last Digit of Year Sealed WW = Week Sealed L = Lot Number = "Green" Packaging 8-Lead SOIC (LG)
8-Lead SOIC 16-Lead SOIC
630mW 1300mW
Top Marking
HV9910BNG
YWW LLLLLLLL
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Bottom Marking
CCCCCCCCC AAA
Y = Last Digit of Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = "Green" Packaging
*May be part of top marking
Thermal Resistance
Package 8-Lead SOIC 16-Lead SOIC ja 128OC/W 82OC/W
16-Lead SOIC (NG)
Electrical Characteristics (The specifications are at T = 25C and V
A
IN
= 12V, unless otherwise noted.)
Sym
Description
Min
Typ
Max
Units
Conditions
Input
VINDC IINSD Input DC supply voltage range1 Shut-Down mode supply current * * 8.0 0.5 450 1.0 V mA DC input voltage Pin PWMD to GND
Internal Regulator
VDD VDD, line
1. * #
Internally regulated voltage Line Regulation of VDD
-
7.25 0
7.5 -
7.75 1.0
V V
VIN = 8.0V, IDD(ext)() = 0, 500pF at GATE; RT = 226k, PWMD = VDD VIN = 8.0 - 450V, IDD(ext) = 0, 500pF at GATE; RT = 226k, PWMD = VDD
Also limited by package power dissipation limit, whichever is lower. VDD load current external to the HV9910B. Denotes the specifications which apply over the full operating ambient temperature range of -40C < TA < +125C. Guaranteed by design.
2
HV9910B
Electrical Characteristics (cont.) (The specifications are at T = 25C and V
A IN
= 12V, unless otherwise noted.)
Internal Regulator (cont.)
Sym VDD, load UVLO UVLO IIN,MAX Description Load regulation of VDD VDD undervoltage lockout threshold VDD undervoltage lockout hysteresis Current that the regulator can supply before IC goes into UVLO * # Min 0 6.45 5.0 Typ 6.7 500 Max 100 6.95 Units mV V mV mA Conditions IDD(ext) = 0 - 1.0mA, 500pF at GATE; RT = 226k, PWMD = VDD VDD rising VDD falling VIN = 8.0V
PWM Dimming
VEN(lo) VEN(hi) REN Pin PWMD input low voltage Pin PWMD input high voltage Pin PWMD pull-down resistance at PWMD * * 2.0 50 100 0.8 150 V V k VIN = 8.0 - 450V VIN = 8.0 - 450V VPWMD = 5.0V
Current Sense Comparator
VCS,TH VOFFSET TBLANK tDELAY Current sense pull-in threshold voltage Offset voltage for LD comparator Current sense blanking interval Delay to output * * 225 213 -12 150 250 250 215 80 275 287 12 280 150 mV mV ns ns -40C < TA < +85C TA < +125C --VLD = VDD, VCS = VCS,TH + 50mV after TBLANK VLD = VDD, VCS = VCS,TH + 50mV after TBLANK RT = 1.00M RT = 226k VGATE = 0V, VDD = 7.5V VGATE = VDD, VDD = 7.5V CGATE = 500pF, VDD = 7.5V CGATE = 500pF, VDD = 7.5V
Oscillator
fOSC Oscillator frequency 20 80 25 100 30 120 kHz
GATE Driver
ISOURCE ISINK tRISE tFALL
1. * #
GATE sourcing current GATE sinking current GATE output rise time GATE output fall time
-
165 165 -
30 30
50 50
mA mA ns ns
Also limited by package power dissipation limit, whichever is lower. VDD load current external to the HV9910B. Denotes the specifications which apply over the full operating ambient temperature range of -40C < TA < +125C. Guaranteed by design.
3
HV9910B
Application Information
The HV9910B is optimized to drive buck LED drivers using open-loop peak current mode control. This method of control enables fairly accurate LED current control without the need for high side current sensing or the design of any closed loop controllers. The IC uses very few external components and enables both Linear and PWM dimming of the LED current. A resistor connected to the RT pin programs the frequency of operation (or the off-time). The oscillator produces pulses at regular intervals. These pulses set the SR flip-flop in the HV9910B which causes the GATE driver to turn on. The same pulses also start the blanking timer which inhibits the reset input of the SR flip flop and prevent false turn-offs due to the turn-on spike. When the FET turns on, the current through the inductor starts ramping up. This current flows through the external sense resistor RCS and produces a ramp voltage at the CS pin. The comparators are constantly comparing the CS pin voltage to both the voltage at the LD pin and the internal 250mV. Once the blanking timer is complete, the output of these comparators is allowed to reset the flip flop. When the output of either one of the two comparators goes high, the flip flop is reset and the GATE output goes low. The GATE goes low until the SR flip flop is set by the oscillator. Assuming a 30% ripple in the inductor, the current sense resistor RCS can be set using: RCS = 0.25V (or VLD) 1.15 ILED (A)
7.5V at the VDD pin. This voltage is used to power the IC and any external resistor dividers needed to control the IC. The VDD pin must be bypassed by a low ESR capacitor to provide a low impedance path for the high frequency current of the output GATE driver. The HV9910B can also be operated by supplying a voltage at the VDD pin greater than the internally regulated voltage. This will turn off the internal linear regulator of the IC and the HV9910B will operate directly off the voltage supplied at the VDD pin. Please note that this external voltage at the VDD pin should not exceed 12V. Although the VIN pin of the HV9910B is rated up to 450V, the actual maximum voltage that can be applied is limited by the power dissipation in the IC. For example, if an 8-pin SOIC (junction to ambient thermal resistance R,j-a = 128C/ W) HV9910B draws about IIN = 2.0mA from the VIN pin, and has a maximum allowable temperature rise of the junction temperature limited to about T = 100C, the maximum voltage at the VIN pin would be:
Constant frequency peak current mode control has an inherent disadvantage - at duty cycles greater than 0.5, the control scheme goes into subharmonic oscillations. To prevent this, an artificial slope is typically added to the current sense waveform. This slope compensation scheme will affect the accuracy of the LED current in the present form. However, a constant off-time peak current control scheme does not have this problem and can easily operate at duty cycles greater then 0.5 and also gives inherent input voltage rejection making the LED current almost insensitive to input voltage variations. But, it leads to variable frequency operation and the frequency range depends greatly on the input and output voltage variation. HV9910B makes it easy to switch between the two modes of operation by changing one connection (see oscillator section).
In these cases, to operate the HV9910B from higher input voltages, a Zener diode can be added in series with the VIN pin to divert some of the power loss from the HV9910B to the Zener diode. In the above example, using a 100V zener diode will allow the circuit to easily work up to 450V. The input current drawn from the VIN pin is a sum of the 1.0mA current drawn by the internal circuit and the current drawn by the GATE driver (which in turn depends on the switching frequency and the GATE charge of the external FET). IIN 1.0mA + QG * fS In the above equation, fS is the switching frequency and QG is the GATE charge of the external FET (which can be obtained from the datasheet of the FET).
Input Voltage Regulator
The HV9910B can be powered directly from its VIN pin and can work from 8.0 - 450VDC at its VIN pin. When a voltage is applied at the VIN pin, the HV9910B maintains a constant
4
HV9910B
Current Sense
The current sense input of the HV9910B goes to the noninverting inputs of two comparators. The inverting terminal of one comparator is tied to an internal 250mV reference whereas the inverting terminal of the other comparator is connected to the LD pin. The outputs of both these comparators are fed into an OR GATE and the output of the OR GATE is fed into the reset pin of the flip-flop. Thus, the comparator which has the lowest voltage at the inverting terminal determines when the GATE output is turned off. The outputs of the comparators also include a 150-280ns blanking time which prevents spurious turn-offs of the external FET due to the turn-on spike normally present in peak current mode control. In rare cases, this internal blanking might not be enough to filter out the turn-on spike. In these cases, an external RC filter needs to be added between the external sense resistor (RCS) and the CS pin. Please note that the comparators are fast (with a typical 80ns response time). Hence these comparators are more susceptible to be triggered by noise than the comparators of the HV9910. A proper layout minimizing external inductances will prevent false triggering of these comparators.
Linear Dimming
The Linear Dimming pin is used to control the LED current. There are two cases when it may be necessary to use the Linear Dimming pin. In some cases, it may not be possible to find the exact RCS value required to obtain the LED current when the internal 250mV is used. In these cases, an external voltage divider from the VDD pin can be connected to the LD pin to obtain a voltage (less than 250mV) corresponding to the desired voltage across RCS. Linear dimming may be desired to adjust the current level to reduce the intensity of the LEDs. In these cases, an external 0-250mV voltage can be connected to the LD pin to adjust the LED current during operation. To use the internal 250mV, the LD pin can be connected to VDD. Note: Although the LD pin can be pulled to GND, the output current will not go to zero. This is due to the presence of a minimum on-time (which is equal to the sum of the blanking time and the delay to output time) which is about 450ns. This will cause the FET to be on for a minimum of 450ns and thus the LED current when LD = GND will not be zero. This current is also dependent on the input voltage, inductance value, forward voltage of the LEDs and circuit parasitics. To get zero LED current, the PWMD pin has to be used.
Oscillator
The oscillator in the HV9910B is controlled by a single resistor connected at the RT pin. The equation governing the oscillator time period tOSC is given by:
PWM Dimming
PWM Dimming can be achieved by driving the PWMD pin with a low frequency square wave signal. When the PWM signal is zero, the GATE driver is turned off and when the PWMD signal if high, the GATE driver is enabled. Since the PWMD signal does not turn off the other parts of the IC, the response of the HV9910B to the PWMD signal is almost instantaneous. The rate of rise and fall of the LED current is thus determined solely by the rise and fall times of the inductor current. To disable PWM dimming and enable the HV9910B permanently, connect the PWMD pin to VDD.
If the resistor is connected between RT and GND, HV9910B operates in a constant frequency mode and the above equation determines the time-period. If the resistor is connected between RT and GATE, the HV9910B operates in a constant off-time mode and the above equation determines the offtime.
GATE Output
The GATE output of the HV9910B is used to drive an external FET. It is recommended that the GATE charge of the external FET be less than 25nC for switching frequencies 100kHz and less than 15nC for switching frequencies > 100kHz.
5
HV9910B
Block Diagram
VIN
Regulator POR
VDD
LD
+ Blanking 250mV + Oscillator RQ S GATE
CS
GND
RT
PWMD
Pin Description
Pin # 8-Lead SOIC 1 2 16-Lead SOIC 1 4 Function VIN CS Description This pin is the input of an 8.0 - 450V linear regulator. This pin is the current sense pin used to sense the FET current by means of an external sense resistor. When this pin exceeds the lower of either the internal 250mV or the voltage at the LD pin, the GATE output goes low. Ground return for all internal circuitry. This pin must be electrically connected to the ground of the power train. This pin is the output GATE driver for an external N-channel power MOSFET. This is the PWM dimming input of the IC. When this pin is pulled to GND, the GATE driver is turned off. When the pin is pulled high, the GATE driver operates normally. This is the power supply pin for all internal circuits. It must be bypassed with a low ESR capacitor to GND (0.1F). This pin is the linear dimming input and sets the current sense threshold as long as the voltage at the pin is less than 250mV (typ). This pin sets the oscillator frequency. When a resistor is connected between RT and GND, the HV9910B operates in constant frequency mode. When the resistor is connected between RT and GATE, the IC operates in constant off-time mode. No connection
3 4
5 8
GND GATE
5
9
PWMD
6 7
12 13
VDD LD
8
14 2, 3, 6, 7, 10, 11, 15, 16
RT
-
NC
6
HV9910B 8-Lead SOIC (Narrow Body) Package Outline (LG)
4.9x3.9mm body, 1.75mm height (max), 1.27mm pitch
D 8 E E1
Note 1 (Index Area D/2 x E1/2) L 1
L2
Gauge Plane
1
L1
Seating Plane
Top View A
Note 1
View B View B
h h
A
A2
Seating Plane
A1
e
b
Side View
A View A-A
Note 1: This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
Symbol MIN Dimension (mm) NOM MAX
A 1.35* 1.75
A1 0.10 0.25
A2 1.25 1.65*
b 0.31 0.51
D 4.80 4.90 5.00
E 5.80 6.00 6.20
E1 3.80 3.90 4.00
e 1.27 BSC
h 0.25 0.50
L 0.40 1.27
L1 1.04 REF
L2 0.25 BSC
0 8
O
1 5O 15O
O
JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005. * This dimension is not specified in the original JEDEC drawing. The value listed is for reference only. Drawings are not to scale.
7
HV9910B 16-Lead SOIC (Narrow Body) Package Outline (NG)
9.90x3.90mm body, 1.75mm height (max), 1.27mm pitch
16
D
1
Note 1 (Index Area D/2 x E1/2)
E1
E
L2 Gauge Plane
1 L1
L
Seating Plane
Top View
A
View B
View B
h A A2 e
Seating Plane
h
Note 1
A1
b A
Side View
View A-A
Note 1: This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
Symbol MIN Dimension (mm) NOM MAX
A 1.35* 1.75
A1 0.10 0.25
A2 1.25 1.65*
b 0.31 0.51
D 9.80 9.90 10.00
E 5.80 6.00 6.20
E1 3.80 3.90 4.00
e 1.27 BSC
h 0.25 0.50
L 0.40 1.27
L1 1.04 REF
L2 0.25 BSC
0O 8
O
1 5O 15O
JEDEC Registration MS-012, Variation AC, Issue E, Sept. 2005. * This dimension is not specified in the original JEDEC drawing. The value listed is for reference only. Drawings are not to scale.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV9910B A031808
8

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